A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
نویسندگان
چکیده
منابع مشابه
A Low Power DDR SDRAM Controller Design
This paper work leads to a working implementation of a Low Power DDR SDRAM Controller that is meant to be used as a reference for future implementations. . The DDR SDRAM is an enhancement to the traditional Synchronous DRAM. It supports data transfers on both edges of each clock cycle, effectively doubling the data throughput of the memory device. In this project Low Power Techniques are propos...
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The application of the synchronous dynamic random access memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price and still high speed memory is needed. Most of the newly developed stand alone embedded devices in the field of image, video and sound processing take more and more use of it. The big amount of low pr...
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ژورنال
عنوان ژورنال: Science China Information Sciences
سال: 2014
ISSN: 1674-733X,1869-1919
DOI: 10.1007/s11432-014-5226-1